A practical DFT checklist for new PCB designs新板设计的实用 DFT 检查清单

Most test problems are designed in long before the first fixture is quoted. The cheapest moment to fix them is at schematic and layout review — once a board is released, every missing test point becomes either a coverage gap or an expensive workaround. This is the checklist we walk through with clients before any board goes to layout.大多数测试问题,早在第一套治具报价之前就已经"设计"进了板子里。修正它们成本最低的时机是原理图与布局评审——板子一旦发出,每一个缺失的测试点不是变成覆盖率缺口,就是变成昂贵的补救措施。下面是我们在客户的板子进入布局前逐项核对的清单。

1. Test-point access一、测试点可达性

• Every electrical net should be probeable. Aim for a dedicated test pad on each net; where space forbids it, document which nets are uncovered and why, so the coverage trade-off is a decision, not a surprise.每个电气网络都应可探测。尽量为每个网络设置专用测试焊盘;空间不允许时,记录哪些网络未覆盖及原因——让覆盖率的取舍成为"决策"而非"意外"。
• Prefer dedicated pads over component lands. Probing directly on component leads or fine-pitch pads risks damage and gives unstable contact over fixture life.优先使用专用测试焊盘,而非元件焊盘。直接探测元件引脚或细间距焊盘既可能造成损伤,长期接触也不稳定。
• Keep test pads on one side where possible. Single-sided access means a simpler, cheaper and more reliable fixture; double-sided fixtures roughly double mechanical complexity.测试焊盘尽量集中在同一面。单面探测意味着治具更简单、更便宜、更可靠;双面治具的机械复杂度大约翻倍。

2. Pad size and spacing二、焊盘尺寸与间距

• Use the largest pad the layout allows. A commonly used rule of thumb is around 0.9–1.0 mm (35–40 mil) diameter for standard probes; smaller pads force fine-pitch probes that wear faster and cost more.在布局允许范围内把焊盘做大。常用经验值是标准探针配约 0.9–1.0 mm(35–40 mil)直径;焊盘更小就只能用细间距探针——磨损更快、成本更高。
• Respect probe pitch. Standard probe grids favour 2.54 mm (100 mil) centres, with 1.27 mm (50 mil) as the usual practical minimum before fixture cost and fragility climb sharply.尊重探针栅格间距。标准探针阵列以 2.54 mm(100 mil)中心距最稳妥;1.27 mm(50 mil)通常是实用下限,再小治具成本与脆弱性会陡增。
• Keep clearance from tall components and the board edge. Probes need room to land and the fixture needs room to clamp — keep test pads away from tall parts and leave a clear margin along board edges for hold-downs and tooling.与高元件和板边保持距离。探针需要落针空间,治具需要压紧空间——测试焊盘要避开高元件,板边预留空白区域给压杆与工装。

3. Tooling and registration三、定位与工装

• Provide at least two tooling holes, unplated, placed diagonally and asymmetrically so the board only fits one way.至少设置两个定位孔——非电镀孔,对角且非对称布置,确保板子只能以唯一方向装入。
• Add fiducials if the line uses optical alignment, and keep panelisation breakaways clear of test pads — pads on break-off rails disappear after depanel.若产线使用光学对位,加基准点(fiducial);拼板工艺边上不要放测试焊盘——分板后这些焊盘就不存在了。

4. Electrical design for coverage四、面向覆盖率的电气设计

• Make resets, enables and boundary-scan pins accessible. A reachable TAP port turns hundreds of digital nets into testable nets at almost zero layout cost.复位、使能与边界扫描引脚必须可达。一个可触达的 TAP 口,几乎零布局代价就能让数百个数字网络变得可测。
• Give the tester a way to isolate power. Test pads on both sides of inrush-limiting elements and the ability to back-drive or disable supplies makes power-rail faults diagnosable instead of mysterious.给测试机隔离电源的手段。在浪涌限制元件两侧都布测试点,并允许禁用或旁路供电,电源轨故障才能被定位,而不是成为悬案。
• Pull-ups, series resistors and unconnected pins: agree the rules early — they decide what an in-circuit tester can and cannot measure.上拉、串阻与悬空引脚:尽早约定处理规则——它们直接决定在线测试机"能测什么、不能测什么"。

5. Review it as a deliverable五、把 DFT 当作交付物来评审

Treat testability as a release criterion: run a coverage estimate at layout review, record the uncovered nets with a reason for each, and have the test engineer sign off alongside the layout engineer. Ten minutes of review at this stage routinely saves weeks at line bring-up.把可测试性当作发布门槛:布局评审时做一次覆盖率估算,逐项记录未覆盖网络及原因,并由测试工程师与布局工程师共同签核。这个阶段十分钟的评审,往往能在产线导入时省下数周。